1) Field of the Invention
The present invention relates to a semiconductor memory device that consists of a ferroelectric memory.
2) Description of the Related Art
A ferroelectric memory is a nonvolatile memory that uses a ferroelectric material for a capacitor film and that stores data by the residual polarization of the ferroelectric material. Since it is unnecessary to use a power supply to hold data, the ferroelectric memory may be applied to a storage device that stores and holds data in an IC card. In the future, multi-purpose IC card obtained by incorporating various applications into a single IC card may be considered. In a multi-purpose IC card of this type, a storage device that consists of a ferroelectric memory (hereinafter “FeRAM”) is considered to be used not only for storing data but also as an application working area.
The flow of the data read processing of a conventional FeRAM is shown in FIG. 1. Namely, data is read from a memory cell to a bit line (step S241), the read data is amplified by a sense amplifier (step S242), the amplified data is output to the outside (step S243), data destructed as a result of data read is written back to the memory cell (step S244), and the bit line is pre-charged with a ground potential to thereby initialize the bit line (step S245). The data write-back operation at the step S244 is referred to as “restore”.
FIG. 2 is a timing diagram for the data read processing of the conventional FeRAM. As shown in FIG. 2, during data reading, an electric potential of a pre-charge signal /PRC is set at a logically low potential level (hereinafter “L level”) and the electric potential of a word line (WL) and that of a plate line driving signal PLCLK are set at a logically high potential level (hereinafter “H level”).
When a sense amplifier driving signal SACLK is set at H level, then the potentials of a pair of bit lines BL and /BL are sensed and the potentials of the bit lines BL and /BL are defined. Thereafter, the voltage of the word line (WL) is boosted to a higher voltage and data is restored. The electric potential of the pre-charge signal /PRC is returned to H level, and the bit lines BL and /BL are pre-charged and initialized.
FIG. 3 shows the configuration of a circuit that boosts the voltage of the word line (WL) in the conventional FeRAM. FIG. 4 is a timing diagram that shows the operation of the circuit shown in FIG. 3. As shown in FIGS. 3 and 4, a first MOS transistor 1 is activated in response to a signal WLBOOT that boots the word line (WL), and an H-level word line enable signal WLE is supplied from a word line driving circuit that is not shown. A second MOS transistor 2 is then activated.
As a result, a signal WLCLOCK supplied from the word line driving circuit, not shown, is supplied to the word line (WL) as a word line driving clock signal WLCLK at the level of a positive power supply potential (hereinafter “VDD”) through a buffer 3, thus charging the word line (WL) almost to the VDD Level. A capacitor 4 that serves as a coupling capacitance is connected to the word line (WL). During a restore operation, a driving signal BOOSTCLK for this capacitor 4 becomes H level and the voltage of the word line (WL) is boosted by capacitance coupling.
In relation to the configuration of the FeRAM, there are two types of word line (WL)-plate line combinations as follows. The first is a one-to-one correspondence type, i.e., a word line WL1 corresponds to a plate line PL1 and a word line WL2 corresponds to a plate line PL2 as shown in FIG. 5. The second is a type that word lines WL1 and WL2 share the plate line PL1 as shown in FIG. 6. FIG. 7 is a circuit diagram that shows the configuration of a circuit that controls word line selection in a conventional plate line shared type FeRAM. FIG. 8 is a timing diagram that shows the operation of the circuit shown in FIG. 7.
As shown in FIGS. 7 and 8, when a block select signal BLOCKSEL becomes H level and an address select signal ADDR_SEL becomes H level, then the output signal of a first NAND gate 10 that inputs the block select signal and the address select signal becomes L level and the output signal is supplied to a first NMOS transistor 11 as an L-level gate signal WLPC1.
In addition, the output signal of the first NAND gate 10 is inverted by a first inverter 12, and the inverted signal is supplied to a third NMOS transistor 14 as an H-level gate signal WLSEL1 GT when a second NMOS transistor 13 inputs the H-level WLBOOT signal and is turned on. The third NMOS transistor 14 is, therefore, turned on. At this moment, when the H-level WLCOCK signal is supplied to the drain of the third NMOS transistor 14 from the word line driving circuit, not shown, a word line driving clock signal WLCLK1L at VDD level is output from the source of the third NMOS transistor 14 to the first word line of the paired word lines that share one plate line. That is, the first word line is selected.
On the other hand, since the address select signal ADDR_SEL is at H level, an address select signal /ADDR_SEL obtained by inverting the address select signal ADDR_SEL becomes L level. The output signal of a second NAND gate 15 that inputs the L-level address select signal ADDR_SEL and the H-level block select signal BLOCKSEL, becomes H level. Therefore, an H-level gate signal WLPC2 is supplied to the gate of a fourth NMOS transistor 16 from the second NAND gate 15, thus turning on the fourth NMOS transistor 16. When this fourth NMOS transistor 16 is turned on, the electric potential of a word line driving clock signal WLCLK2L for the second word line of the paired word lines that share one plate line becomes a ground potential, thus turning the second word line into an unselected state.
At this moment, the output signal of the second NAND gate 15 is inverted by a second inverter 17 and the output signal becomes L level. This L-level signal is supplied to a sixth NMOS transistor 19 as a gate signal WLSEL2GT when a fifth NMOS transistor 18 inputs the H-level WLBOOT signal and is turned on. As a result, the sixth NMOS transistor 19 is turned off, thereby preventing the H-level WLCOCK signal supplied from the word line driving circuit, not shown, from being output as the word line driving clock signal WLCLKI2L for the second word line.
As explained above, the FeRAM may be used as an application working area in a multi-purpose IC card or the like in the future. When so, even though the operation of an application is finished and the supply of power that has been supplied to the FeRAM during the operation is stopped, data being subjected to the operation remains in the FeRAM. To prevent unintended data from being leaked from this working area, it is necessary to delete unnecessary data or overwrite meaningless data so as to destruct the unnecessary data. This disadvantageously requires complicated procedures. Further, since the latch of the sense amplifier is inverted when inverting and restoring an arbitrary bit of data, power is disadvantageously, wastefully consumed.
There is conventionally known a system for securing safety by presetting the upper limit of a failure frequency for access authentication and recording an access authentication failure frequency so as to prevent data from being accessed by illegal means. However, since this upper limit may possibly be manipulated, this conventional system is not always omnipotent.